The invention relates to a shift register unit applied in a shift register, and in particular to a shift register employed in drivers of display panels.
FIG. 1 is a schematic diagram of a conventional liquid crystal display (LCD) panel. As shown in FIG. 1, LCD panel 1 comprises display array 10, data driver 11, and scan driver 12. Display array 10 comprises a plurality of pixels. Data driver 11 controls a plurality of data lines D1 to Dn, and scan driver 12 controls a plurality of scan lines S1 to Sm. Scan driver 12 sequentially outputs scan signals SD1 to SDm to scan lines S1 to Sm in response to a scan control signal to turn on the pixels corresponding to a row. When a row of pixels are turned on, data driver 11 outputs corresponding video signals with gray scale values to n pixels corresponding to the row through data lines D1 to Dn. Each of data driver 11 and scan driver 12 requires a shift register to output signals, sequentially.
Typically, a shift register comprises a plurality of identical, substantially cascaded, shift register units. For example, in a shift register of a scan driver, an output signal of each shift register unit is transmitted to a next shift register unit as its input signal and to a corresponding row of pixels through a scan line.
FIG. 2 shows a conventional shift register as disclosed in U.S. Pat. No. 4,084,106. Shift register 2 comprises two identical, substantially cascaded, shift register units 21 and 22. Clock signals CK and XCK are provided to shift register units 21 and 22, respectively. Clock signals CK and XCK have inverse phases. Each shift register unit 21 or 22 comprises input and output terminals, transistors T21 to T26, and capacitors C21 and C22. Output terminal OUT1 of shift register unit 21 is coupled to input terminal IN2 of shift register unit 22. Referring to FIGS. 2 and 3, shift register unit 21 is given as an example. In period P1, input signal IS1 and clock signal XCK are at high logic level (first state), and clock signal CK is at low logic level. Transistor T23 is thus turned on, and capacitor C21 is charged to high logic level, so that node N21 is at high logic level. Since the gate of transistor T22 is coupled to node N21, transistor T22 is turned on. Output terminal OUT1 outputs output signal OS1 at low logic level to input terminal IN2 as input signal IS2 of shift register unit 22.
In a subsequent period P2, input signal IS1 and clock signal XCK are transformed to being at low logic level, and clock signal CK is transformed to being at high logic level. Transistor T23 is thus turned off. Node N21, which is at high voltage level, has higher voltage due to the parasitic capacitance of transistor T22. Output signal OS1 is transformed to being at high logic level. However, in practice, transistor T23 may operate in the sub-threshold region or turned-off region to generate unexpected leakage current. Node N21 does not remain at high logic level, and transistor T22 is not continuously turned on. Thus, output signal OS1 does not continuously remain at high logic level, resulting in false operation of shift register unit 22 and the timing of shift register 2 is in error.